In recent times, with development and advancement of semiconductor manufacturing technologies, semiconductor devices continuously advance toward high integration and high speed and can be used in a variety of products from large home appliances to small mobile products.
To increase data processing speed of such semiconductor memory devices, a Single Data Rate (SDR) memory device, a Double Data Rate (DDR) memory device, a DDR2 memory device and the like have been developed and a cycle of a clock signal has become shorter and shorter. Also, control methods for increasing an operation speed of internal circuits have continuously been studied.
FIG. 1 is a block diagram illustrating a configuration of a data input circuit of a conventional semiconductor memory device.
The data input circuit illustrated in FIG. 1 includes a sense amplifier enable signal generating unit 500 and a data sensing unit 600.
The sense amplifier enable signal generating unit 500 receives a clock signal CLK and first through fourth command signals CMD<1:4>, and generates a sense amplifier enable signal SAEN. More specifically, the sense amplifier enable signal generating unit 500 receives the first through fourth command signals CMD<1:4>, generates a write command, delays the write command by a write latency (WL) and 3 cycles of the clock signal CLK, and generates the sense amplifier enable signal SAEN. The write latency means a delay time until external data is actually inputted to a data pad after input of the write command.
Meanwhile, the data sensing unit 600 multiplexes first through fourth align data ADIN<1:4> based on first through fourth sense amplifier selection signals SASEL<1:4>, senses the multiplexed data in response to the sense amplifier enable signal SAEN, and transfers the sensed data to first through fourth global lines GIO1-GIO4. The first through fourth align data ADIN<1:4> are aligned by synchronizing externally inputted data with a data strobe signal. Since the external data is inputted synchronously with a rising edge and a falling edge of the data strobe signal, when a burst length (BL) is four, four data are aligned in synchronization with a second falling edge of the data strobe signal. In other words, it takes 1.5 cycles of the clock signal CLK to align the data.
Meanwhile, the data strobe signal is toggled after an amount of time corresponding to the write latency and tDQSS. The tDQSS is a delay time from a rising edge of a clock signal at which the write command is inputted to a first rising edge of the data strobe signal. This is for compensating a difference in a delay time corresponding to a length of a line in a semiconductor memory device that transfers the clock signal CLK and a delay time corresponding to a line that transfers the data strobe signal when they do not exactly correspond to each other. In general, the tDQSS is defined as 0.75˜1.25 cycles of the clock signal CLK.
If the WL is 1, the BL is 4 and the tDQSS is the maximum, i.e., 1.25 cycles of the clock signal CLK, it takes 3.75 cycles of the clock signal CLK until the external data is aligned synchronously with the data strobe signal. However, since the data sensing unit 600 can sense first through fourth align data ADIN<1:4> and transfer the sensed data to the first through fourth global lines GIO1-GIO4 after the external data is aligned synchronously with the data strobe signal, the sense amplifier enable signal SAEN should be enabled after the external data is aligned. In order to ensure such time margin, the sense amplifier enable signal SAEN is enabled after the write latency and 3 cycles of the clock signal CLK from the input of the write command.
Meanwhile, in order to increase the operation speed of a semiconductor memory device, the recent trend is to reduce a tWTR by advancing a time point at which a read command is inputted after a write operation. The tWTR is a delay period from a time just after the write operation to a time just before the read command is inputted, and is ensured so that a read operation can be started after data is sufficiently stored in a corresponding cell upon the write operation. In other words, the reduction of the tWTR by advancing the time point of the input of the read command can increase the operation speed of a semiconductor memory device, but may cause data loss since the read operation can be started in a state that a sufficient amount of charge is not stored in the cell.